DESIGN AND EVALUATION OF AREA-EFFICIENT PIPELINED TURBO ENCODER AND DECODER
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Abstract
In this project design and evaluation of area efficient pipelined turbo encoder and decoder is
implemented. Turbo coding is very effective technique for correcting errors. These codes widely used in communication systems. Wireless communications (3G & 4G) includes turbo codes within it for accurate error correction. Earlier, the polar codes are implemented using 8 bits, so polar decoder is restricted by the inherent iterative process to compile the data at a higher rate. High decoding accuracy is the major flaw of polar coding implementation. Hence in this work, implementing 64-bit turbo encoder and decoder to compile the data at higher rate with reduced area and delay. The system is implemented and correlated in Application Specific Integrated Circuit (ASIC). At last compared with existed system, proposed system gives effective outcome in terms of delay and area.
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