Implementation of FPGA accelerator architecture for Convolution Neural Network in Emotional Recognition System

Abstract

The field of deep learning, artificial intelligence has arisen due to the later advancements in computerized innovation and the accessibility of data information, has exhibited its ability and adequacy in taking care of complex issues in learning that were not previously conceivable. The viability in emotional detection and acknowledging specific applications have demonstrated by Convolution neural networks (CNNs). In any case, concentrated Processor activities and memory transfer speed are necessitated that cause general CPUs to neglect to accomplish the ideal degrees of execution. Subsequently, to build the throughput of CNNs, equipment quickening agents utilizing General Processing Units (GPUs), Field Programmable Gate Array (FPGAs) and Application Specific Integrated circuits (ASICs) has been used. We feature the primary highlights utilized for productivity improving by various techniques for speeding up. Likewise, we offer rules to upgrade the utilization of FPGAs for the speeding up of CNNs. The proposed algorithm on to an FPGA platform and show that emotions recognition utterance duration 1.5s is identified in 1.75ms, while utilizing 75% of the resources. This further demonstrates the suitability of our approach for real-time applications on Emotional Recognition system.