An Energy Dissipation and Cell Optimization of Vedic Multiplier Topologies for Nanocomputing Applications

Abstract

Quantum-dot cellular automata is a cutting edge enumeration methodology that suggests less area and high speed
compare CMOS methodology. The CMOS circuitry having issues related to short channel and device density so QCA is better
and powerful alternative to reduce the area as well as increase the speed of the circuitry. QCA could be a modern computing
innovation that’s made of quantum cell containing two electrons and dots. A multiplier is a vital part of Digital Signal
Processing (DSP) and many more digital circuits applications. We emphasize Vedic multiplier topologies structures agreeing
to Vedic science from old Indian figures. In this article, we suggested a efficient, less complex Vedic 22 and 44 multipliers
topologies using proposed ultra efficient Half Adder (HA), Full Adder (FA) topologies in QCADesigner simulation
environment for less energy and fast speed for nano computing application. The simulation waveform suggests an architecture
outstrip in comparison to the parameters of cell count, area, latency related to past QCA layouts. The proposed QCA 22
Vedic multiplier design shown 37.62% improvement in QCA cell count and 44 Vedic multiplier design shown 71.72%
improvement in cell counts as well as 29.62% area is decreased for 22 QCA Vedic multiplier and 43.38% area decreased
from 4 4 QCA Vedic multiplier as related to its best existing designs.