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The use of FFT is very efficient in the field of digital signal processing and communication. It is one of the finest operations in the area of digital signal processing. Verilog implementation of floating point FFT with reduced generation logic is the proposed architecture, where the two inputs and outputs of any butterfly can be exchanged all data and addresses in FFT dispensation can be reordered. The Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT) It as the most important numerical algorithm of our lifetime. The Decimation- In-Time radix-2 FFT using butterfly structure has been designed with optimized area and power. The butterfly operation is faster. The outputs of the shorter transforms are reused to compute many outputs thus, the all-computational cost becomes less. The 8-bit input FFT is synthesized using Verilog. The simulation result and the implementation details such as design summary, RTL schematic and others can be noticed. This paper reports the area, delay and power analysis of 8-point FFT by developing a Verilog model in cadence tool kit. The implementation of fast algorithm for the DFT for evaluating their performance. The performance of this algorithm by implementing them on the cadence virtuoso digital design by developing our own FFT processor architecture.
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