Design and Implementation of low power Fault Tolerant Hybrid Full Swing Full Adder for Neural Network Applications

Abstract

Neural Networks (NN) are algorithms that can recognize relationships between data and can mimic the operation of the human brain. Some neurons are not fault free. Hence system that is fault tolerant is designed. Fault tolerance is one of the major factors that has to be considered while designing the VLSI circuit for critical applications. Implementation of a full adder using pass transistor logic has resulted in output degradation and CMOS logic has resulted in high power consumption. The fidelity of the sum output and carry output affects the fault tolerant capability of the full adder Hence the aim of this work is to design and implement hybrid low power full adder with full swing at carry out. The proposed full swing full adder will be used to implement fault tolerant Self Repairing full adder. Fault tolerant Self Repairing full adder helps to detect the fault in the circuit and resolve the single and double faults. For the proposed system, even though the number of transistors is increased by 4 for the Hybrid one bit full adder and 4 for the Self Repairing full adder, the output swing is maintained as per the requirement but the power consumed is reduced by 15.4% for Hybrid full adder and 27.4% for self-repairing full adder.