DESIGN AND DEVELOPMENT OF ENHANCED MEMORY RELIABILITY AGAINST MULTIPLE CELL UPSETS USING DMC
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Abstract
Transient multiple cell upsets (MCUs) are beginning to seriously affect the reliability of memories when they are exposed to radiation settings. More complex error correction codes (ECCs) are often used to protect memory and prevent data corruption caused by MCUs; nevertheless, their primary drawback is an increase in delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The two error correction codes and the fact that not all situations lead to an improvement in mistake correction skills are the main issues. This work proposes a revolutionary decimal matrix code (DMC) based on the divide-symbol to provide better memory reliability with minimal delay overhead. The proposed DMC uses the decimal algorithm to provide the maximum amount of error detection capability. Furthermore, to minimize the area overhead of extra circuits without interfering with the encoding and decoding processes, it is advised to implement the encoder-reuse method (ERT)
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