Enhanced 2-Bit Binary Magnitude Comparator Design using Pass Transistor Logic for Improved Speed and Power Efficiency
Main Article Content
Abstract
This research presents the design of a 2-bit binary Magnitude Comparator (MC) using Conventional CMOS (CCMOS) logic and Pass Transistor Logic (PTL). The proposed MC design is subjected to simulation and compared with five other existing MC designs to assess its performance. The results indicate that the proposed 2-bit MC design exhibits significant improvements in terms of speed and power efficiency. This enhancement results in a notable improvement in the Power Delay Product (PDP). As a result, the proposed MC design stands as a highly effective alternative to existing designs. The rapid evolution of circuit design has introduced various methodologies for VLSI circuit implementation, including CCMOS, PTL, and Transmission Gate Logic (TGL). Consequently, various MC designs have been developed to meet diverse requirements. The PTL-based 2-bit MC design utilizes 40 transistors; however, it suffers from voltage degradation, especially in lower CMOS technology nodes, leading to reduced drive power. To address these issues, new designs have emerged.
Downloads
Metrics
Article Details
Licensing
TURCOMAT publishes articles under the Creative Commons Attribution 4.0 International License (CC BY 4.0). This licensing allows for any use of the work, provided the original author(s) and source are credited, thereby facilitating the free exchange and use of research for the advancement of knowledge.
Detailed Licensing Terms
Attribution (BY): Users must give appropriate credit, provide a link to the license, and indicate if changes were made. Users may do so in any reasonable manner, but not in any way that suggests the licensor endorses them or their use.
No Additional Restrictions: Users may not apply legal terms or technological measures that legally restrict others from doing anything the license permits.