Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications

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K.V.K.V.L Pavan Kumar et.al

Abstract

The paper outlines the utmost importance of energy-efficient devices for IoT applications and recommends adual edge-triggeredTSPC flip-flop in fully-static mode at 45nm technology with low supply rail carried out in CMOS using MENTOR GRAPHICS tool.The proposed flip-flop proved to be energy efficient compared to traditional double and single edge-triggered flip-flops in terms of latency, power, the figure of merit and area for IoT applications. A comparison of two types of dual-edge triggered flip-flops are analyzed concerning the mentioned performance metrics and deduces the best flip-flop for IoT applications. Clock overlap issues are turning down in dual edge-triggered TSPC flip-flopcompared with a conventional dual edge-triggered flip-flop in full static modeand allow stringent operation at 1V supply rail thatdelivers1.14uW power, 0.60fJ figure of merit and 531.99ps latency at 45nm CMOS

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How to Cite
et.al, K. P. K. (2021). Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications. Turkish Journal of Computer and Mathematics Education (TURCOMAT), 12(3), 3055–3063. Retrieved from https://www.turcomat.org/index.php/turkbilmat/article/view/1340
Section
Research Articles