Design of 16-Bit SAR ADC Using DTMOS Technique

Main Article Content

Yarlagadda Archana et.al

Abstract

This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

Downloads

Download data is not yet available.

Metrics

Metrics Loading ...

Article Details

How to Cite
et.al, Y. A. (2021). Design of 16-Bit SAR ADC Using DTMOS Technique. Turkish Journal of Computer and Mathematics Education (TURCOMAT), 12(3), 3046–3054. Retrieved from https://www.turcomat.org/index.php/turkbilmat/article/view/1339
Section
Research Articles