Implementation Of Power Efficient Accurate And Approximate Full Adders For Image Processing Applications
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Abstract
In Integrated circuits (IC)s system Computational performance is limited by its performance and since the execution time is dominated by the multiplication factor because of that high-speed adder is much more important in DSP systems. This paper presents an efficient full adder design in CMOS 25nm technology using footed quasi resistance-based gate diffusion input (FQR-GDI). This design uses a smaller number of transistors than the conventional CMOS based Adder designs. By employing the FQR-GDI technique there is an extensive decrease in power and delay of the circuit. Design also solves the threshold drops problem of Original GDI cell resulting in better output signals. The proposed methodology implemented in Tanner Tools using TSMC library.
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