Optimization of a Stochastic Number Generator Using D Flip Flop

Abstract

Escalating development in science and technology with exponential demand for gadgets and devices towards smart, intelligent and effective implementation for sustainable livelihood is the need of the society. The demand has fueled for improvising hardware and its design for enhanced computational speed, less latency, less power consumption, low cost involved in fabricating these hardware components. One such approach is stochastic computing, although developed long back, still the field is at naïve and rudimentary stage mandatory incorporation of latest circuit techniques and methodologies. The objective of our study is to incorporate D-Flip Flops (DFFs) within the stochastic number generator (SNG) architecture and assess the performance of stochastic circuit to break haven the cost involved in hardware fabrication, power consumption etc. Our study compared the positioning of DFFs within and outside SNG and compare the power consumption and area occupancy relating with efficiency. Experimental investigations revealed that DFFs within the SNG architecture was more optimal, effective and efficient, catering the needs and objectives of our study. Since our investigations is at preliminary stage, further warranting and validation is sought to take over to next stage of implementation.